1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to a buffer circuit that enables signal transmission to be performed at high speed and with improved duty cycle distortion.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Buffers can be implemented as part of an integrated circuit. For example, many integrated circuits include a core section and an input/output (“I/O”) section. The I/O section may be arranged near the periphery of the integrated circuit for receiving signals forwarded to, or alternatively, for providing additional drive strength to signals forwarded from, the integrated circuit. In other examples, buffers may be used within the core section between subsystems to provide timing and drive strength matching between those subsystems. Regardless of its placement, a buffer can be formed as either a separate discrete element or within various portions of an integrated circuit.
A typical buffer may utilize one or more Complementary Metal Oxide Semiconductor (“CMOS”) inverters, depending on whether the buffer is intended to operate as an inverting or non-inverting buffer. As shown in FIG. 1, non-inverting buffer 100 can be implemented by coupling two CMOS inverters between a power supply and a ground supply. Each of the CMOS inverters may include a p-channel MOSFET (“PMOS” transistor) and an n-channel MOSFET (“NMOS” transistor). Within a single inverter, the gate terminals of the two MOSFETs (or MOS Field Effect Transistors) may be connected together to receive an input signal, while the drain terminals are connected to form the output. In the example of FIG. 1, the output (VA) of the first CMOS inverter (transistors P1, N1) is connected to the input of the second CMOS inverter (transistors P2, N2), so that the signal (VOUT) output from the buffer circuit 100 may be a substantially equal, albeit somewhat delayed, version of the input signal (VIN) received by the buffer circuit 100. In some cases, a propagation delay through the buffer circuit may be increased by cascading additional pairs of CMOS inverters with those shown in FIG. 1. In other cases, the input signal may be inverted by implementing the buffer circuit with an odd number of CMOS inverters.
In operation, buffer circuit 100 may receive an input value (VIN) at gate terminals of the first CMOS inverter for activating only one of the transistors P1 and N1. For example, NMOS transistor N1 may be activated with a logic high input value, whereas PMOS transistor P1 may be activated with a logic low input value. Once activated, the selected transistor will either pull-up (if P1 is activated) or pull-down (if N1 is activated) the intermediate node voltage (VA) to a logic high or logic low value, respectively.
Because buffer 100 is a non-inverting buffer circuit, the transistor activated in the second CMOS inverter stage will be doped opposite to the transistor activated in the first CMOS inverter stage. For example, if a logic high value received at the first CMOS inverter stage activates transistor N1, transistor P2 will be activated in the second CMOS inverter stage with a logic low value at the intermediate node (VA) to provide an output value (VOUT) that is similar, if not equal, to the input value (VIN). As will be described in more detail below, however, relative differences between the n-channel and p-channel threshold values may introduce undesirable delays within the output signal.
In some cases, variations in supply voltage, temperature or process may cause the trip point (i.e., the voltage threshold at which the output value transitions from one logic state to another) of a buffer circuit to deviate from an ideal or intended value. For example, an ideal buffer may have a trip point set at VDD/2 for a low input voltage level of 0 volts and a high input voltage level of VDD volts. However, process variations, such as variations in the threshold values of n-channel and p-channel transistors, may cause the trip point to deviate from VDD/2, thereby changing the propagation delay between low-to-high transitions (i.e., rising edges) and/or high-to-low transitions (i.e., falling edges) of the output signal.
If a buffer circuit imparts inconsistent amounts of delay to the rising and falling edges of the output signal, the output signal will experience duty cycle distortion. In general, duty cycle distortion may appear whenever the delays between rising and falling edges of an output signal are inconsistent, or momentarily fluctuates over time. The effects of duty cycle distortion on a buffered signal are illustrated in the examples of FIGS. 2 and 3.
In some instances, the “duty cycle” of a signal may be described as the ratio of high time (i.e., the time over which the signal is high) to the overall period of the signal. As shown in FIG. 2, for example, the duty cycle of the input signal (VIN) 200 may be substantially equal to tH(IN)/TIN, where tH(IN) is the high time and TIN is the period of the input signal. Though duty cycle specifications are often application-specific, desirable duty cycle values may range between about ±2-5% of 50%.
In general, duty cycle distortion may occur when there are time delay differences between: (i) the rising edge of the input signal and the rising edge of the output signal, (ii) the rising edge of the input signal and the falling edge of the output signal, (iii) the falling edge of the input signal and the rising edge of the output signal, and (iv) the falling edge of the input signal and the falling edge of the output signal. In particular, duty cycle distortion may occur between (i) and (iv) if the output signal is not inverted, and between (ii) and (iii) if the output is inverted. In some cases, duty cycle distortion (“DCD”) may be further described as the difference between the output duty cycle (e.g., Y %) and the input duty cycle (e.g., X %), or (Y−X) %. Acceptable levels of duty cycle distortion may range between about 0% DCD and about 5% DCD, depending on the application.
In some cases, an output signal (VOUT) may avoid duty cycle distortion by ensuring that the time delay between rising edges (tR) and the time delay between the falling edges (tF) of the input and output signals are consistent and substantially equal, as shown in FIG. 2. In other words, FIG. 2 illustrates an ideal case in which the duty cycle (tH(OUT)/TOUT) of the output signal 250 is made substantially equal to the duty cycle (tH(IN)/TIN) of the input signal 200 by avoiding duty cycle distortion between the input and output signals.
In other cases, duty cycle distortion may be introduced into the output signal (VOUT) when the time delays between rising and falling edges of the input and output signals are not equal, as shown in FIG. 3. In particular, FIG. 3 illustrates the case in which a substantially longer time delay (tF) is imparted between the falling edges, than the time delay (tR) imparted between the rising edges, of the input signal 300 and the output signal 350. The longer falling edge time delay may be due, in part, to the increased propagation delay of the falling edge transition of the output signal. In some cases, the increased propagation delay may be caused by variations in supply voltage, temperature and/or manufacturing process. For example, variations in a transistor threshold voltage, or variations in the voltage supplied to the transistor, may reduce the amount of current conducted by the transistor, thereby increasing a propagation delay through the transistor and decreasing the speed with which a buffer circuit may transition from a logic high to a logic low value. Thus, in addition to increasing the duty cycle of the output signal (relative to the input duty cycle), the increased propagation delay decreases the maximum frequency with which the buffer circuit may operate.
For at least these reasons, it would be beneficial to provide an improved buffer circuit that minimizes (or altogether eliminates) duty cycle distortion to provide an output signal duty cycle that is substantially equal to the duty cycle of an input signal supplied to the buffer circuit. The improved buffer circuit may do so by ensuring substantially equal time delays between the rising and falling edges of the input and output signals, thereby maintaining a maximum operating frequency of the buffer circuit. In addition, the improved buffer circuit may achieve minimum duty cycle distortion even with changes in supply voltage, temperature and process.